Overview

Interrupts, although their implementation depends of the microcontroller/processor, can be explained in a general manner.

Interrupts are features to drive the processor for different kind of events. One example of their principal use is to prioritize real time event (time critical events) over the main program.

The different features that interrupts encapsulate are:

  1. Interrupt. Asynchronous signal that external devices trigger over the processor.
  2. Exceptions. Logical or conditional software error that can be also used for debugging purposes.
  3. Trap. Synchronous internal interruption made by the processor.

If the design of the processor determines the having of a special pin for interruptions, then the processor requires some way to identify the interruption (where it came from). In this way the devices and peripheral can share interruptions, and the processor will require knowing which device triggers the interruption in order to process it.

Interruptions has “attributes” to determine its priority, disabling state, edge sensibility, level sensibility, and other custom “attributes” that are based in the specific processor.

Priorities

Each processor has priorities among its interruptions in the case that multiple interruptions happen in the same time. By priority, the processor determines which interruption dispatch first. For example (1):

 

Image result for interrupt priority

 

The interruption priority can be set by HW or SW or both. For example, for HW, the microcontroller might have a pin specialized for high priority peripherals. By SW, the processor has an algorithm to determine priority.

Disabling State

Maskable interrupt are the interrupt that can be disabled based in the design of the processor. Maskable interrupt can be masked individually or in grups.

Non maskable interrupts are high priority interrupt that cannot be disabled. As you can see in the Image (1) Non-maskable interrupt are just below Reset.

It is important that if you disable interrupts, you should reenable them to avoid unexpected behaviors.

Edge Sensibility

Edge Sensibility determines if the processor shall trigger an interrupt when it detects a transition from LOW to HIGH or a transition from HIGH to LOW.

This transition is made by the interrupt controller which indicates to the processor to dispatch the interrupt until a new transition is performed.

Level Sensibility

Level Sensibility determines if the processor shall maintain the interrupt active during a certain time. When it is maintained in HIGH state or it is maintaned in LOW state.

This state is maintained by the interrupt controller which indicates the processor to maintain the interrupt during certain time.

External References

(1) https://infocenter.nordicsemi.com/index.jsp?topic=%2Fsds_s140%2FSDS%2Fs1xx%2Fprocessor_avail_interrupt_latency%2Fexception_mgmt_sd.html

 

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